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ZY8160 60A DC-DC Intelligent POL
8V to 14V Input ? 0.5V to 2.75V Output
Data Sheet
4.5
Signal Specifications
Parameter
VDD
Conditions/Description
Internal supply voltage
Min
3.15
Nom
3.3
Max
3.45
Units
V
SYNC/DATA Line (SD pin)
ViL_sd
ViH_sd
Vhyst_sd
VoL
Tr_sd
Cnode_sd
Ipu_sd
Freq_sd
Tsynq
T0
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current @ 0.5V
Maximum allowed rise time 10/90%VDD
Added node capacitance
Pull-up current source at Vsd=0V
Clock frequency of external SD line
Sync pulse duration
Data=0 pulse duration
-0.5
0.75 x
VDD
0.25 x
VDD
14
0.3
475
22
72
5
0.3 x VDD
VDD + 0.5
0.45 x
VDD
60
300
10
1.0
525
28
78
V
V
V
mA
ns
pF
mA
kHz
% of clock
cycle
% of clock
cycle
ADDR0…ADDR4 Inputs
ViL_x
ViH_x
Vhyst_x
RdnL_ADDR
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
External pull down resistance
ADDRX forced low
-0.5
0.7 x VDD
0.1 x VDD
0.3 x VDD
VDD+0.5
0.3 x VDD
10
V
V
V
kOhm
Power Good and OK Inputs/Outputs
Iup_PG
Iup_OK
ViL_x
ViH_x
Vhyst_x
IoL
Pull-up current source input forced low PG
Pull-up current source input forced low OK
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current at 0.5V
25
175
-0.5
0.7 x VDD
0.1 x VDD
4
110
725
0.3 x VDD
VDD+0.5
0.3 x VDD
20
μ A
μ A
V
V
V
mA
Current Share Bus (CS pin)
Iup_CS
ViL_CS
ViH_CS
Vhyst_CS
IoL
Tr_CS
ZD-01674 Rev. 1.2, 02-Jul-10
Pull-up current source at VCS = 0V
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current at 0.5V
Maximum allowed rise time 10/90% VDD
www.power-one.com
0.84
-0.5
0.75 x
VDD
0.25 x
VDD
14
3.1
0.3 x VDD
VDD+0.5
0.45 x
VDD
60
100
Page 7 of 30
mA
V
V
V
mA
ns
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